A phase-change memory element is a memory element for storing information using the characteristics of electric conductivity or a resistance difference between a crystalline phase and an amorphous phase of a specific phase-change material. The phase-change memory element forms a memory cell electrically connected to a transistor element or the like, formed on a semiconductor substrate for addressing and read/write operations of the device. In the memory element, information is stored using a conductivity difference in accordance with the phase-change of a memory layer, and data is stored in the phase-change memory element including a phase-change region.
FIG. 1A and FIG. 1B illustrate a conventional phase-change memory cell 10. As seen in FIG. 1A, the phase-change memory cell includes a phase-change material 14 between a top electrode 12 and a bottom electrode 18. To increase the current density and, thereby, improve the efficiency of heating of the phase-change material 14, the bottom electrode 18 may be connected to the phase-change material 14 through a bottom electrode contact (BEC) 16 that has reduced surface area in comparison to the bottom electrode 18. An access transistor 20 may be connected to the bottom electrode 18 and controlled by a word line (WL).
As seen in FIGS. 1A, 1B and 2, the phase-change memory cell 10 operates such that a current flowing through the phase-change material 14 electrically heats a phase-change region, and the structure of the phase-change material 14 is reversibly changed to a crystalline state (FIG. 1A) or an amorphous state (FIG. 1B) to store information. The stored information can be read by flowing a relatively low current through the phase-change region and measuring the resistance of the phase-change material.
In setting the phase-change material layer 14 to an amorphous state or a crystalline state, different pulses may be used to control the heating of the phase-change material layer. As seen in FIG. 3, a high temperature short duration heating cycle 35 is used to reset the phase-change material 14 to an amorphous state and a longer duration lower temperature heating cycle 36 is used to set the phase-change material 14 to a crystalline state. In particular, in the short duration cycle 35, the phase-change material 14 is heated to a temperature above the melting point, Tm, of the phase-change material and then quickly cooled, e.g., within a few nanoseconds, to create an amorphous region in the phase-change material 14. In the longer duration cycle 36, the phase-change material 14 is heated to a temperature above a crystallizing point, Tx, and below the melting point, Tm, of the phase-change material and maintained at that temperature for a predetermined time before cooling to create a crystallized region in the phase-change material 14. Thus, the temperature is maintained within a set window of above the crystallizing temperature Tx and below the melting temperature Tm.
FIG. 4 is a graph of the voltage-current relationship for a typical phase-change material 14. As seen in FIG. 4, the graph is divided into a reset state, 1, and a set state, 3, for a read operation and a section, 2, for programming the state of the phase-change material 14. Thus, in reading the phase-change material, states 1 or 3, the current to voltage relationship is linear based on the resistance of the phase-change material. However, the programming section, 2, is non-linear. Accordingly, to program the phase-change material 14 the voltage is increased to above the threshold voltage and the current increases to the minimum programming current non-linearly.
In an array of memory cells, the different memory cells may have different threshold voltages and, accordingly, different minimum set currents. Thus, as seen in FIG. 4, for different cells, reflected in the lines labeled i, ii and iii, the threshold voltage and the minimum set current may vary. However, conventionally, all the memory cells are typically programmed with substantially the same current.
Furthermore, as seen in FIGS. 5A and 5B, a conventional phase-change memory device 500 may have difficulty controlling the voltage applied to the memory cells to assure that all of the memory cells exceed the threshold voltage. As seen in FIG. 5A, a current mirror controls the current supplied to program the memory cells 510 such that the cell current ICELL is controlled by the reference current IREF. During programming from the reset state to the set state, if a voltage lower than the threshold voltage Vth of the phase-change material 14 is supplied to the phase-change material 14, the voltage level of the data line DL is close to the level of the power supply voltage VDD. If the amount of set current ICELL supplied to the PCM is increased by increasing the reference current IREF, a level of the voltage supplied to the PCM may be increased beyond the threshold voltage Vth. Thus, the resistance of the phase-change material changes to the dynamic resistance and the voltage level of the data line DL becomes lower than the level of the power supply voltage VDD. Such a change in voltage may be problematic where the different memory cells have different threshold voltages and may cause some cells to not be set if the same current is applied to all the cells as the voltage may not reach the threshold voltage, reduction of reset current may also cause difficulty in fitting the set current into the narrowed set window and it may be difficult to maintain the voltage and/or current in the set window as illustrated in FIG. 5B for all of the devices.